In general, a flash memory may refer to a nonvolatile memory that retains stored data even without a power supply, and have a function to electrically delete and re-write data in a chip partially or completely. The deletion of data stored in the flash memory may be performed in a block unit as well as in the entire chip, however, cannot be performed in a byte unit.
Many kinds of the flash memories have been developed according to a physical structure of a cell acting as a basic unit in storing data. As representative examples for the flash memory, a Not OR (NOR)-type flash memory used for storing a code and a Not AND (NAND)-type flash memory used for storing data may be given.
As to the NOR-type flash memory, code execution may be possible due to random access of a byte unit similar to the existing static Random Access Memory (SRAM) or Read Only Memory (ROM). However, the NOR-type flash memory may disadvantageously have a relatively low program speed and be disadvantageous for high integration. Conversely, the NAND-type flash memory may have a relatively fast program speed and be advantageous for high integration, however, does not allow random access and has an interface different from the existing SRAM or ROM.
As a result, the NAND-type flash memory capable of realizing the high integration may be widely used in a storage system. The NAND type flash memory may support read and program operations of a page unit (2 KB or 512 KB), and an erase operation of a block unit (128 KB or 16 KB) by itself, which does not provide compatibility with an interface for driving a general memory by a processor. In a conventional art for solving the above-described problems, an interface device for controlling the NAND-type flash memory in a memory interface scheme of the processor has been suggested.
FIG. 1 is a block diagram illustrating a system for controlling a flash memory based on a conventional interface device.
A conventional flash memory control device may merely act as an interface device 130 for providing only the interface compatibility between a processor 110 and a NAND flash memory 140, and thus supporting either only write/read operations of a page unit and erase operation of a block unit, or write/read operations for simultaneously writing/reading a number of pages or a erase operation for simultaneously erasing a number of blocks in a sequential fashion.
However, the conventional flash memory control devices may be required to inform about the corresponding command and address and participate in the data transmission each time the processor 110 requests the interface device 130 to perform an operation. Such a larger overhead in the processor has been known as a main factor for causing a bottleneck phenomenon to occur in the performance of the flash memory based-storage system.
Also, when a number of chips are present in the storage system, the processor 110 is required to participate in performance improvement obtained by utilizing parallelism between chips in the conventional flash memory control device. However, the parallelism of a chip unit cannot be appropriately utilized due to the bottleneck phenomenon on a system bus and a relatively slow program speed.
Also, in a structure of the conventional flash memory control system, a one-unit operation is required to be completed before performing the following unit operation, and therefore an operation already performed is required to be first completed even with respect to another operation with a relatively higher priority determined by a user, which results in an increase in a delay time with respect to a request of the storage system.
Accordingly, a system and method for controlling a flash memory according to the present invention are suggested, which may read/write and erase data by controlling a flash memory even without separate participation of the processor, thereby controlling the flash memory in parallel in a plurality of modules.